Ethernet IP Lead
AMD · Bangalore · 8+ yrs experience · Posted 2026-03-30
Tech stack: C++
About the role
Seeking a seasoned engineer with deep expertise in system software and computer architecture.
You will lead the design and development of Ethernet/NIC diagnostics system software spanning pre‑silicon and post‑silicon environments across all AMD embedded SoCs.
In this role, you will operate as a technical lead, working closely with developers, architects, and cross‑functional stakeholders to define diagnostic strategies, drive execution excellence, and resolve complex system‑level issues.
KEY
Responsibilities:
- Drive high‑quality planning and implementation of Ethernet/NIC diagnostics test cases with strong emphasis on coverage, scalability, and maintainability.
- Own complex debug efforts, including deep root‑cause analysis of diagnostic test failures, and drive them to resolution in partnership with design and silicon teams.
- Collaborate closely with architecture, IP design, firmware, BIOS, validation, and platform software teams.
- Ensure Ethernet/NIC diagnostics readiness for silicon bring‑up, post‑silicon validation, and field debug scenarios.
- Mentor mid‑level engineers in diagnostics development, debugging techniques, and system‑level thinking.
Qualifications:
- Expert‑level proficiency in C++ and system‑level software development.
- Strong experience in post‑silicon diagnostics development and validation.
- Deep understanding of networking protocols, including IEEE 802.3, TCP, UDP, IPv4 & IPv6.
- Hands‑on experience validating NIC hardware IP for 1G / 5G / 10G / 25G Ethernet.
- Proficiency with networking and debug tools such as Wireshark, tcpdump, iperf (iperf2/iperf3).
- Solid understanding of PC hardware platforms, including SoCs, chipsets, BIOS, firmware, and graphics subsystems.
- Strong knowledge of x86 architecture, PCIe, and system interconnects.
- Good understanding of OS internals and hardware‑software interactions.
- Strong grasp of the software development life cycle and quality best practices.
- Excellent analytical, problem‑solving, and debugging skills.
- Clear, effective communication skills; fluent in written and spoken English.
- Bachelor’s degree with 8+ years of relevant industry experience, or
- Master’s degree with 6+ years of relevant industry experience
- Preferred majors: Computer Science, Electronics, Electrical Engineering, or related fields.
Qualifications
- Expert‑level proficiency in C++ and system‑level software development.
- Strong experience in post‑silicon diagnostics development and validation.
- Deep understanding of networking protocols, including IEEE 802.3, TCP, UDP, IPv4 & IPv6.
- Hands‑on experience validating NIC hardware IP for 1G / 5G / 10G / 25G Ethernet.
- Proficiency with networking and debug tools such as Wireshark, tcpdump, iperf (iperf2/iperf3).
- Solid understanding of PC hardware platforms, including SoCs, chipsets, BIOS, firmware, and graphics subsystems.
- Strong knowledge of x86 architecture, PCIe, and system interconnects.
- Good understanding of OS internals and hardware‑software interactions.
- Strong grasp of the software development life cycle and quality best practices.
- Excellent analytical, problem‑solving, and debugging skills.
- Clear, effective communication skills; fluent in written and spoken English.
- Bachelor’s degree with 8+ years of relevant industry experience, or
- Master’s degree with 6+ years of relevant industry experience
- Preferred majors: Computer Science, Electronics, Electrical Engineering, or related fields.
Responsibilities
- Drive high‑quality planning and implementation of Ethernet/NIC diagnostics test cases with strong emphasis on coverage, scalability, and maintainability.
- Own complex debug efforts, including deep root‑cause analysis of diagnostic test failures, and drive them to resolution in partnership with design and silicon teams.
- Collaborate closely with architecture, IP design, firmware, BIOS, validation, and platform software teams.
- Ensure Ethernet/NIC diagnostics readiness for silicon bring‑up, post‑silicon validation, and field debug scenarios.
- Mentor mid‑level engineers in diagnostics development, debugging techniques, and system‑level thinking.