Lead DFx Silicon Design Engineer

AMD · Bengaluru · 12+ yrs experience · Posted 2026-05-07

Tech stack: C, C++, Linux, Unix

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About the role

AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.
As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
KEY
Responsibilities:
- Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology.
- Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
- Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS.
- Writing and maintain DFT documentation and specifications.
- Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
- Performing scan insertion, ATPG verification and test pattern generation
- Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.
Qualifications:
- Experience in DFT design, integration, verification, ATPG and Silicon Debug experience.
- Demonstrated technical leadership and works well with cross-functional teams.
- Excellent communication and interpersonal skills
- Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc.
- Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
- Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
- Experience in solving logic design or timing issues with integration, synthesis and PD teams.
- Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
- Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis.
- Knowledge of ATE and digital IC manufacturing test is a plus.
- Strong problem-solving skills.
- Team player with strong communication skills.
- Bachelor’s or Master’s degree in electrical/Electronic Engineering with 12+Yrs of exp

Qualifications

- Experience in DFT design, integration, verification, ATPG and Silicon Debug experience.
- Demonstrated technical leadership and works well with cross-functional teams.
- Excellent communication and interpersonal skills
- Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc.
- Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
- Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
- Experience in solving logic design or timing issues with integration, synthesis and PD teams.
- Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
- Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis.
- Knowledge of ATE and digital IC manufacturing test is a plus.
- Strong problem-solving skills.
- Team player with strong communication skills.
- Bachelor’s or Master’s degree in electrical/Electronic Engineering with 12+Yrs of exp

Responsibilities

- Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology.
- Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
- Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS.
- Writing and maintain DFT documentation and specifications.
- Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
- Performing scan insertion, ATPG verification and test pattern generation
- Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.

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