SOC verification Manager/Lead
AMD · Bengaluru · 20+ yrs experience · Posted 2026-06-02
Tech stack: Python
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About the role
SOC verification Manager/Lead Job Summary We are seeking an experienced and highly motivated Verification experts to lead verification activities for complex SoC designs. The ideal candidate will have deep expertise in SoC-level verification, power management verification, low-power verification methodologies, and SoC verification architecture development. This role involves defining verification strategies, architecting scalable verification environments, driving functional and power-aware verification closure, and mentoring verification teams across multiple projects.
Responsibilities:
- Define and drive the overall SoC verification strategy for complex multi-billion transistor SoCs.
- Architect and develop scalable, reusable, and robust SoC verification environments using industry-standard methodologies.
- Lead end-to-end verification planning, execution, coverage closure, and sign-off activities.
- Drive power management verification, including validation of power state transitions, power controllers, reset sequencing, clock management, and power domain interactions.
- Lead low-power verification using UPF/CPF methodologies and ensure compliance with low-power design intent.
- Develop and review verification architectures, test plans, assertions, checkers, scoreboards, and coverage models.
- Collaborate closely with architecture, RTL design, firmware, emulation, validation, and physical design teams.
- Drive debug and root-cause analysis of complex SoC-level issues.
- Establish verification best practices, automation frameworks, and verification metrics.
- Support verification across simulation, emulation, FPGA prototyping, and post-silicon validation environments.
- Mentor and technically lead a team of verification engineers.
- Participate in design reviews and contribute to architecture discussions from a verification perspective.
- Required Skills & Qualifications
- Technical Expertise
- 12–20 years of experience in VLSI Design Verification with a strong focus on SoC verification.
- Proven experience in:
- SoC-Level Verification
- SoC Verification Architecture
- Power Management Verification
- Low-Power Verification
- Functional Verification and Coverage Closure
- Expertise in SystemVerilog and UVM-based verification methodologies.
- Hands-on experience with assertion-based verification (SVA).
- Deep understanding of:
- Power domains
- Retention strategies
- Isolation techniques
- Level shifters
- Dynamic voltage and frequency scaling (DVFS)
- Power state management
- Preferred Skills
- Exposure to firmware-assisted verification and hardware/software co-verification.
- Scripting proficiency in Python, Perl, or Shell.
- Leadership Expectations
- Provide technical leadership for large verification programs.
- Drive verification methodology improvements and standardization.
- Mentor and develop junior and senior verification engineers.
- Influence architecture and design decisions through verification insights.
- Collaborate with global cross-functional teams to ensure successful project execution.
Qualifications:
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field.
Qualifications
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field.
Responsibilities
- Define and drive the overall SoC verification strategy for complex multi-billion transistor SoCs.
- Architect and develop scalable, reusable, and robust SoC verification environments using industry-standard methodologies.
- Lead end-to-end verification planning, execution, coverage closure, and sign-off activities.
- Drive power management verification, including validation of power state transitions, power controllers, reset sequencing, clock management, and power domain interactions.
- Lead low-power verification using UPF/CPF methodologies and ensure compliance with low-power design intent.
- Develop and review verification architectures, test plans, assertions, checkers, scoreboards, and coverage models.
- Collaborate closely with architecture, RTL design, firmware, emulation, validation, and physical design teams.
- Drive debug and root-cause analysis of complex SoC-level issues.
- Establish verification best practices, automation frameworks, and verification metrics.
- Support verification across simulation, emulation, FPGA prototyping, and post-silicon validation environments.
- Mentor and technically lead a team of verification engineers.
- Participate in design reviews and contribute to architecture discussions from a verification perspective.
- Required Skills & Qualifications Technical Expertise
- 12–20 years of experience in VLSI Design Verification with a strong focus on SoC verification.
- Proven experience in: SoC-Level Verification
- SoC Verification Architecture
- Power Management Verification Low-Power Verification
- Functional Verification and Coverage Closure
- Expertise in SystemVerilog and UVM-based verification methodologies.
- Hands-on experience with assertion-based verification (SVA).
- Deep understanding of: Power domains Retention strategies Isolation techniques Level shifters
- Dynamic voltage and frequency scaling (DVFS)
- Power state management
- Exposure to firmware-assisted verification and hardware/software co-verification.
- Scripting proficiency in Python, Perl, or Shell.
- Leadership Expectations Provide technical leadership for large verification programs.
- Drive verification methodology improvements and standardization.
- Mentor and develop junior and senior verification engineers.
- Influence architecture and design decisions through verification insights.
- Collaborate with global cross-functional teams to ensure successful project execution.