Staff - Pre-Silicon System Performance
Qualcomm · Bengaluru · 10+ yrs experience · Posted 2026-04-10
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About the role
Qualcomm India Private Limited
Engineering Group, Engineering Group > Systems Engineering
Responsibilities: - The Senior Staff Engineer in the Server SoC Performance Team is a technical leader responsible for owning end-to-end system performance strategy, methodology, and sign-off for complex server-class SoCs.
- This role drives architecture-level performance insights and influences product and architecture decisions.
- Own system-level performance sign-off across multiple subsystems and use cases.
- Define and drive performance methodology and benchmarks for pre-silicon and early silicon platforms.
- Lead deep-dive investigations involving CPU, memory, NoC, IO, and power-performance trade-offs.
- Translate architecture features into quantitative performance projections and risks.
- Influence architecture and design trade-offs.
- Mentor engineers and act as a technical authority.
Qualifications: - Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 10+ years of industry experience in SoC/System performance, architecture, or validation.
- Strong expertise in SoC micro-architecture, memory systems, and interconnects.
- Master’s degree or PhD (or equivalent experience).
- Extensive experience with RUMI/emulation-based performance sign-off.
- Preferred experience in Server-class / Data Center SoC architecture, including cache-coherent interconnects (e.g., CHI/ACE-class fabrics), scalable memory hierarchies, and high-bandwidth IO subsystems (PCIe/CXL-class), with ability to translate architecture features into performance sign-off metrics and system-level debug.
- Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.
- Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.
- PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
- Level of Responsibility
- Works independently with significant impact on product performance and program success.
Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 10+ years of industry experience in SoC/System performance, architecture, or validation.
- Strong expertise in SoC micro-architecture, memory systems, and interconnects.
- Master’s degree or PhD (or equivalent experience).
- Extensive experience with RUMI/emulation-based performance sign-off.
- Preferred experience in Server-class / Data Center SoC architecture, including cache-coherent interconnects (e.g., CHI/ACE-class fabrics), scalable memory hierarchies, and high-bandwidth IO subsystems (PCIe/CXL-class), with ability to translate architecture features into performance sign-off metrics and system-level debug.
- Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.
- Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.
- PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
- Level of Responsibility
- Works independently with significant impact on product performance and program success.
Responsibilities
- The Senior Staff Engineer in the Server SoC Performance Team is a technical leader responsible for owning end-to-end system performance strategy, methodology, and sign-off for complex server-class SoCs.
- This role drives architecture-level performance insights and influences product and architecture decisions.
- Own system-level performance sign-off across multiple subsystems and use cases.
- Define and drive performance methodology and benchmarks for pre-silicon and early silicon platforms.
- Lead deep-dive investigations involving CPU, memory, NoC, IO, and power-performance trade-offs.
- Translate architecture features into quantitative performance projections and risks.
- Influence architecture and design trade-offs.
- Mentor engineers and act as a technical authority.