Senior Design Verification Engineer
AMD · Hyderabad · Posted 2026-06-17
Tech stack: Linux, Python
About the role
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment
Responsibilities:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment
Qualifications:
- be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause and work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics and modify or add tests or constrain random tests to meet the coverage requirements
- Proficient in IP level ASIC verification
- Proficient in debugging RTL code using simulation tools
- Expert in UVM concepts and SystemVerilog language
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced in developing UVM‑based verification frameworks and testbenches, processes, and flows
- Comfortable automating workflows in a distributed compute environment
- Exposure to simulation profile, efficiency improvement, acceleration, and formal verification
- Scripting language experience: Perl, Python, Makefile, shell
- Exposure to leadership or mentorship
- Prior exposure to networking protocols such as Ethernet, UAL, LLR, and CBFC
- Experienced in using AI tools
- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science preferred
Qualifications
- be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause and work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics and modify or add tests or constrain random tests to meet the coverage requirements
- Proficient in IP level ASIC verification
- Proficient in debugging RTL code using simulation tools
- Expert in UVM concepts and SystemVerilog language
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced in developing UVM‑based verification frameworks and testbenches, processes, and flows
- Comfortable automating workflows in a distributed compute environment
- Exposure to simulation profile, efficiency improvement, acceleration, and formal verification
- Scripting language experience: Perl, Python, Makefile, shell
- Exposure to leadership or mentorship
- Prior exposure to networking protocols such as Ethernet, UAL, LLR, and CBFC
- Experienced in using AI tools
- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science preferred
Responsibilities
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment