GPU Performance Modeling & Optimization Engineer

AMD · Bengaluru · 5–10 yrs experience · Posted 2026-06-19

Tech stack: C++, Linux, Python

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About the role

We are seeking an experienced, hands-on GPU Performance Modeling and Optimization Engineer to join our core engineering team. Your primary focus will be pre-silicon performance modeling, feature exploration, and workload optimization, coupled with owning post-silicon characterization, hardware-software correlation, and lab-based performance debug.
You will be responsible for ensuring our upcoming SoCs/GPUs deliver best-in-class performance across both traditional graphics pipelines (compute shaders, ray tracing, rasterization) and cutting-edge compute/AI workloads (Transformer-based models, Large Language Models (LLMs), Vision models etc).
Key
Responsibilities:
- 1. Pre-Silicon Performance Modeling & Feature Exploration
- Simulator: Leverage and maintain highly accurate, modular cycle-accurate or cycle-approximate simulators for key GPU subsystems (e.g., Shader Engines, Cache Hierarchies, Memory Subsystems, and Interconnects).
- Microarchitectural Exploration: Define and execute rigorous simulation experiments to evaluate proposed GPU configurations, scaling limits, and trade-offs.
- Provide data-driven recommendations backed by thorough sensitivity analyses.
- Workload Characterization: Trace, analyze, and profile complex workloads to extract structural execution footprints. Translate these insights into microarchitectural bottlenecks and establish bounding box for performance for various workloads.
- 2. Hardware-Software Co-Design & Workload Optimization
- Compute & LLM Scaling Optimization: Profile and optimize performance for advanced generative AI and LLM topologies. Identify bottlenecks across the compute engine, local memory hierarchy (L1/L2), and SoC fabrics.
- Graphics Stack Optimization:
- Analyze execution efficiency across graphics shaders and compute-heavy pipelines to maximize execution unit utilization and minimize latency.
- Cross-Layer Collaboration: Partner with compiler, runtime, and software framework teams (e.g., PyTorch, Triton) to implement/recommend optimizations.
- 3. Post-Silicon Characterization, Correlation & Debug
- Pre-to-Post Correlation: Lead efforts to execute workloads on early silicon, capture performance telemetry, and systematically correlate results back to pre-silicon performance models to improve simulator fidelity.
- Lab Debug & Telemetry: Root-cause hardware-software execution mismatches and unexpected performance drops on physical silicon using low-level performance counters, register dumps, and Linux tracing frameworks.
- Cross-Functional Alignment: Act as the technical bridge between hardware design (RTL) and software stacks, translating high-level workload requirements into clear hardware architectural constraints.
- Preferred Experience & Skills:
- GPU Architecture Depth: Excellent technical knowledge of GPU execution pipelines, SIMD/SIMT models, cache hierarchy management, memory technologies, and high-bandwidth interconnects (e.g., PCIe, custom fabrics).
- Advanced Performance Modeling: Strong, hands-on experience building or significantly contributing to execution-driven/cycle-accurate hardware performance simulators. Expert proficiency in modern C++ and production-grade Python.
- Workload Domain Expertise:
- AI/Compute: Practical understanding of LLM scaling techniques, parallel training/inference strategies (Tensor, Pipeline, Data parallelism), and kernel execution graphs.
- Graphics: Solid grounding in modern programmable graphics pipelines and compute shader mechanics.
- Profiling & Post-Si Debugging: Proven capability to extract and analyze low-level hardware performance counters, profile system workloads under Linux, and work within a lab environment for silicon characterization.
- Delivery & Execution: Excellent structured problem-solving skills.
- Ability to translate raw, noisy simulation or silicon data into crisp, actionable technical findings for engineering stakeholders.
- Academic Credentials & Experience
Qualifications:
- B.E. / B.Tech. / M.Tech. / with 5 to 10 years of industry experience in silicon performance engineering, GPU modeling, or microarchitecture design.

Qualifications

- B.E. / B.Tech. / M.Tech. / with 5 to 10 years of industry experience in silicon performance engineering, GPU modeling, or microarchitecture design.

Responsibilities

- Pre-Silicon Performance Modeling & Feature Exploration
- Simulator: Leverage and maintain highly accurate, modular cycle-accurate or cycle-approximate simulators for key GPU subsystems (e.g., Shader Engines, Cache Hierarchies, Memory Subsystems, and Interconnects).
- Microarchitectural Exploration:
- Define and execute rigorous simulation experiments to evaluate proposed GPU configurations, scaling limits, and trade-offs.
- Provide data-driven recommendations backed by thorough sensitivity analyses.
- Workload Characterization: Trace, analyze, and profile complex workloads to extract structural execution footprints.
- Translate these insights into microarchitectural bottlenecks and establish bounding box for performance for various workloads.
- Hardware-Software Co-Design & Workload Optimization
- Compute & LLM Scaling Optimization: Profile and optimize performance for advanced generative AI and LLM topologies.
- Identify bottlenecks across the compute engine, local memory hierarchy (L1/L2), and SoC fabrics.
- Graphics Stack Optimization:
- Analyze execution efficiency across graphics shaders and compute-heavy pipelines to maximize execution unit utilization and minimize latency.
- Cross-Layer Collaboration: Partner with compiler, runtime, and software framework teams (e.g., PyTorch, Triton) to implement/recommend optimizations.
- Post-Silicon Characterization, Correlation & Debug Pre-to-Post Correlation:
- Lead efforts to execute workloads on early silicon, capture performance telemetry, and systematically correlate results back to pre-silicon performance models to improve simulator fidelity.
- Lab Debug & Telemetry: Root-cause hardware-software execution mismatches and unexpected performance drops on physical silicon using low-level performance counters, register dumps, and Linux tracing frameworks.
- Cross-Functional Alignment: Act as the technical bridge between hardware design (RTL) and software stacks, translating high-level workload requirements into clear hardware architectural constraints.
- Preferred Experience & Skills:
- GPU Architecture Depth: Excellent technical knowledge of GPU execution pipelines, SIMD/SIMT models, cache hierarchy management, memory technologies, and high-bandwidth interconnects (e.g., PCIe, custom fabrics).
- Advanced Performance Modeling:
- Strong, hands-on experience building or significantly
- contributing to execution-driven/cycle-accurate hardware performance simulators.
- Expert proficiency in modern C++ and production-grade Python.
- Workload Domain Expertise:
- AI/Compute: Practical understanding of LLM scaling techniques, parallel training/inference strategies (Tensor, Pipeline, Data parallelism), and kernel execution graphs.
- Graphics: Solid grounding in modern programmable graphics pipelines and compute shader mechanics.
- Profiling & Post-Si Debugging:
- Proven capability to extract and analyze low-level hardware performance counters, profile system workloads under Linux, and work within a lab environment for silicon characterization.
- Delivery & Execution: Excellent structured problem-solving skills.
- Ability to translate raw, noisy simulation or silicon data into crisp, actionable technical findings for engineering stakeholders.
- Academic Credentials & Experience

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