DFT Engineer - 8+ yrs
Cisco · Bangalore · 8–10 yrs experience · Posted 2026-06-22
Tech stack: Python
About the role
Join the Cisco Silicon One team and drive innovation at the heart of next-generation network devices—Cisco Silicon One™. Our unique team operates in a startup-like environment within a world-class corporation, pushing the boundaries of advanced silicon technologies. Our design center brings together all silicon hardware and software development disciplines, promoting an atmosphere of collaboration, technical leadership, and excellence.
We are transforming the networking industry and building the future of the internet for the 5G era. With Cisco Silicon One™, we deliver a unified, programmable silicon architecture—the foundation of all Cisco’s future routing products. Our platform offers high-speed networking, programmability, power efficiency, and scalability for service provider and web-scale markets.
Responsibilities:
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
- You are an ASIC Design for Test Hardware Engineer with 8-10 years of related work experience with a broad mix of technologies.
Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8-10 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience with Jtag protocols, Scan insertion and ATPG.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience working with Gate level simulation, debugging with VCS and other simulators.
- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills: Tcl, Python/Perl.
- Test Static Timing Analysis
- Post silicon validation using DFT patterns. raining: Completed all mandatory corporate trainings, including Fraudulent Applicants, Insider Threats, and BSCC guidelines, to ensure operational compliance.
Qualifications
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8-10 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Experience with Jtag protocols, Scan insertion and ATPG.
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
- Experience working with Gate level simulation, debugging with VCS and other simulators.
- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills: Tcl, Python/Perl.
- Test Static Timing Analysis
- Post silicon validation using DFT patterns.
- raining: Completed all mandatory corporate trainings, including Fraudulent Applicants, Insider Threats, and BSCC guidelines, to ensure operational compliance.
Responsibilities
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
- You are an ASIC Design for Test Hardware Engineer with 8-10 years of related work experience with a broad mix of technologies.