Leadership Role - Emulation

AMD · Hyderabad · 15+ yrs experience · Posted 2026-07-10

Tech stack: Linux, Python

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About the role

AMD is seeking a Principal Member of Technical Staff (PMTS) to lead SoC Emulation for next-generation AMD SOC products. This role is responsible for defining emulation strategy, driving technical execution, and delivering robust, high-performance emulation platforms that enable early software development and de-risk silicon.
Responsibilities:
- Technical Leadership & Strategy
- Own the SoC emulation strategy for one or more major AMD SoC programs
- Define emulation scope, milestones, and success criteria aligned with program and silicon schedules
- Serve as the technical authority for emulation methodology, performance, and debug
- Influence SoC architecture and RTL decisions to improve emulation efficiency and debuggability
- Hands-On Emulation Execution
- Lead bring-up of full-chip and subsystem emulation on enterprise emulation platforms (e.g., Palladium, Veloce, Zebu)
- Integrate RTL, memory models, testbenches, transactors, and software interfaces
- Enable early firmware, BIOS, OS, driver, and application software development
- Debug complex, cross-layer issues spanning RTL, firmware, and software
- Drive performance optimization, capacity planning, and resource utilization of emulation platforms
- Cross-Functional Influence
- Partner closely with SoC design, DV, firmware, software, post-silicon, and architecture teams
- Act as the single-point technical owner for emulation deliverables and readiness
- Provide clear technical status, risk assessment, and mitigation plans to leadership
- Support customer, platform, and ecosystem enablement use cases as needed
- Infrastructure, Methodology & Scale
- Define and drive automation, CI/regressions, and reuse across emulation environments
- Establish best practices for emulation bring-up, debug, and software enablement
- Mentor senior and junior engineers; raise overall emulation capability within AMD
- Evaluate and deploy new tools, flows, and technologies to improve time-to-value
Qualifications:
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience in SoC design, verification, emulation, or HW/SW co-development
- Deep hands-on experience with SoC-level emulation platforms (Palladium, Veloce, Zebu, or equivalent)
- Strong understanding of complex SoC architectures (CPU, GPU, interconnects, memory subsystems, IO)
- Expertise in SystemVerilog/Verilog and scripting (Python, Perl, Tcl, Bash, etc.)
- Proven ability to debug and resolve complex RTL and HW/SW interaction issues
- Demonstrated technical leadership across large, multi-team programs
- Experience enabling Linux/UEFI/BIOS/RTOS bring-up on pre-silicon platforms
- Knowledge of PCIe, DDR, AMBA/CHI, cache coherency, virtualization, and power management
- Experience with co-emulation, acceleration, or hybrid verification environments
- Background in high-performance computing, graphics, AI, or server-class SoCs
- Track record of influencing architecture and validation strategy at the program level

Qualifications

- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience in SoC design, verification, emulation, or HW/SW co-development
- Deep hands-on experience with SoC-level emulation platforms (Palladium, Veloce, Zebu, or equivalent)
- Strong understanding of complex SoC architectures (CPU, GPU, interconnects, memory subsystems, IO)
- Expertise in SystemVerilog/Verilog and scripting (Python, Perl, Tcl, Bash, etc.)
- Proven ability to debug and resolve complex RTL and HW/SW interaction issues
- Demonstrated technical leadership across large, multi-team programs
- Experience enabling Linux/UEFI/BIOS/RTOS bring-up on pre-silicon platforms
- Knowledge of PCIe, DDR, AMBA/CHI, cache coherency, virtualization, and power management
- Experience with co-emulation, acceleration, or hybrid verification environments
- Background in high-performance computing, graphics, AI, or server-class SoCs
- Track record of influencing architecture and validation strategy at the program level

Responsibilities

- Technical Leadership & Strategy
- Own the SoC emulation strategy for one or more major AMD SoC programs
- Define emulation scope, milestones, and success criteria aligned with program and silicon schedules
- Serve as the technical authority for emulation methodology, performance, and debug
- Influence SoC architecture and RTL decisions to improve emulation efficiency and debuggability
- Hands-On Emulation Execution
- Lead bring-up of full-chip and subsystem emulation on enterprise emulation platforms (e.g., Palladium, Veloce, Zebu)
- Integrate RTL, memory models, testbenches, transactors, and software interfaces
- Enable early firmware, BIOS, OS, driver, and application software development
- Debug complex, cross-layer issues spanning RTL, firmware, and software
- Drive performance optimization, capacity planning, and resource utilization of emulation platforms Cross-Functional Influence
- Partner closely with SoC design, DV, firmware, software, post-silicon, and architecture teams
- Act as the single-point technical owner for emulation deliverables and readiness
- Provide clear technical status, risk assessment, and mitigation plans to leadership
- Support customer, platform, and ecosystem enablement use cases as needed
- Infrastructure, Methodology & Scale
- Define and drive automation, CI/regressions, and reuse across emulation environments
- Establish best practices for emulation bring-up, debug, and software enablement
- Mentor senior and junior engineers; raise overall emulation capability within AMD
- Evaluate and deploy new tools, flows, and technologies to improve time-to-value

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