Senior SerDes Verification Engineer

AMD · Bengaluru · Posted 2026-07-17

Tech stack: Python

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About the role

Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
Responsibilities:
- Verification of SerDes Designs:
- Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
Qualifications:
- Solid understanding of SerDes architectures, link training, and equalization.
- Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).
- Familiarity with hardware description languages (HDL) like VHDL or Verilog.
- Strong analytical, problem-solving, and communication skills.
- Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.
- Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.
- Experience with Python, Perl, or similar scripting languages for automation.
- Exposure to high-speed memory interface design and verification, including DDR controller IP verification.
- Functional coverage, assertions knowledge in SV/UVM.
- Ability to work in a fast-paced environment and manage multiple verification tasks.
- Strong team player with good interpersonal and communication skills.

Qualifications

- Solid understanding of SerDes architectures, link training, and equalization.
- Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).
- Familiarity with hardware description languages (HDL) like VHDL or Verilog.
- Strong analytical, problem-solving, and communication skills.
- Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.
- Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.
- Experience with Python, Perl, or similar scripting languages for automation.
- Exposure to high-speed memory interface design and verification, including DDR controller IP verification.
- Functional coverage, assertions knowledge in SV/UVM.
- Ability to work in a fast-paced environment and manage multiple verification tasks.
- Strong team player with good interpersonal and communication skills.

Responsibilities

- Verification of SerDes Designs:
- Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.
- Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).

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