DFT Design Engineer

AMD · Bengaluru · 8+ yrs experience · Posted 2026-07-24

Tech stack: C, Linux, Unix

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About the role

It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.
As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
KEY
Responsibilities:
- Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
- Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
- Work with multi-functional teams and handling schedules
- Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
- Performing scan insertion, ATPG verification and test pattern generation
- Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.
Qualifications:
- Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST
- Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
- Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
- Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
- Familiar with Verilog design language, Verilog simulator and waveform debugging tools
- Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus
- Strong problem-solving skills.
- Team player with strong communication skills.
- Bachelor’s or Master’s degree in electrical/Electronic Engineering with 8+Yrs

Qualifications

- Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, memory BIST/repair or Logic BIST
- Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
- Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
- Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl)
- Familiar with Verilog design language, Verilog simulator and waveform debugging tools
- Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus
- Strong problem-solving skills.
- Team player with strong communication skills.
- Bachelor’s or Master’s degree in electrical/Electronic Engineering with 8+Yrs

Responsibilities

- Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
- Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
- Work with multi-functional teams and handling schedules
- Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
- Performing scan insertion, ATPG verification and test pattern generation
- Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.

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