Senior Lead Verification Engineer
AMD · Bengaluru · 12+ yrs experience · Posted 2026-06-05
Tech stack: Ruby
Apply on the company site · Get a referral for this role
AMD salary & ratings · AMD interview process · More live openings
About the role
The preferred candidate will have proven experience verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment.
KEY
Responsibilities:
- Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture. Understand TestBench Architecture and develop expertise in TestBench Verification Components. Mentor junior engineers.
Qualifications:
- Proficient in IP or Sub-system level ASIC verification
- Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar.
- Exposure to RTL design, software development, formal verification, or other related domains.
- Experience in UVM TestBench Development for complex designs preferred.
- 12+ years of industry experience is preferred
- Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering
Qualifications
- Proficient in IP or Sub-system level ASIC verification
- Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar.
- Exposure to RTL design, software development, formal verification, or other related domains.
- Experience in UVM TestBench Development for complex designs preferred.
- 12+ years of industry experience is preferred
- Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering
Responsibilities
- Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects.
- Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
- Understand TestBench Architecture and develop expertise in TestBench Verification Components.
- Mentor junior engineers.