IP/Subsystem Verification Lead
AMD · Bengaluru · Posted 2026-06-11
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About the role
As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.
You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication
Responsibilities:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
- Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
- Build the directed and random verification tests
- Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality
Qualifications:
- collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Qualifications
- collaborating with other engineers located in different sites/time zones.
- You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Responsibilities
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
- Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
- Build the directed and random verification tests
- Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality