Debug Lead Engineer

AMD · Bengaluru · 15+ yrs experience · Posted 2026-06-22

Tech stack: C, Python

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About the role

Roles & Responsibilities for Lead System Engineer: Assume technical responsibility from Pre-silicon to Post-silicon environment for Feature enablement and SoC-System level flow for use cases. Pre-Silicon: New SOC features enablement, implementation and coverage plan in Emulation Pre-silicon: Review all Silicon bugs that deferred out SOC Tape out and ensure it does not impact the system level features / use cases.
Responsibilities:
- Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts.
- Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path.
- Drive meetings for issue closures and actively track schedules and milestone quality metrics
- Ensure the Best-in-class Documentation and collateral delivery from the team.
Qualifications:
- Highly skilled engineering professional with over 15 years of experience.
- Solid experience in both Pre and Post Silicon enablement and validation with strong BIOS/FW/SW intercepting knowledge.
- Solid Experience and Knowledge in the HW and FW aspects of X86 design
- Solid experience in connecting the bigger picture across different related domains between Hardware/Firmware and Software and com
- Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans
- Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution.
- Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW.
- Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects.
- Experience in Power Management
- Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc.
- Preferred experience with scripting using TCL, Python
- Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills.

Qualifications

- Highly skilled engineering professional with over 15 years of experience.
- Solid experience in both Pre and Post Silicon enablement and validation with strong BIOS/FW/SW intercepting knowledge.
- Solid Experience and Knowledge in the HW and FW aspects of X86 design
- Solid experience in connecting the bigger picture across different related domains between Hardware/Firmware and Software and com
- Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans
- Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution.
- Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW.
- Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects.
- Experience in Power Management
- Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc.
- Preferred experience with scripting using TCL, Python
- Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills.

Responsibilities

- Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts.
- Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path.
- Drive meetings for issue closures and actively track schedules and milestone quality metrics
- Ensure the Best-in-class Documentation and collateral delivery from the team.

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